1. Field of the Invention
The present invention relates to an image generating method and apparatus for printing bit images according to data input from a data processor such as a host computer.
2. Description of the Related Art
As is well known, data sent from a data processor to a printer is comprised of image data for bit map images to be printed out and control data for controlling the print method and mode of a print engine of the printer. In conventional systems, a single processor or controller is used to transform image data into bit map images to be printed out and to send the bit map images to the print engine. In a conventional controller, a memory buffer which is controlled so as to form a First-in First-out (FIFO) memory by software is used for internal data flow in order to synchronize data input from the data processor with data to be outputted to the print engine.
Data input from an external data processor is stored in a register buffer temporarily and the stored data is read out by the controller. The controller executes so called packet processing asynchronously from the input of data in order to memorize packet data into the FIFO memory.
In the packet processing, protocol analysis, pre-editing of image data, transformation of data into packets (intermediate codes) according to the result of pre-editing which makes imaging of bit images onto a bit map memory easier and memorizing intermediate codes into a memory are carried out sequentially. During the pre-editing of image data, respective print positions of individual image data are determined according to the result of the protocol analysis. Accordingly, intermediate codes representing image data include pattern codes of image data and addresses for imaging individual bit images on the bit map memory. Upon output by the controller, the controller transforms intermediate codes into bit images and writes them on the bit map memory.
In a system wherein data processing in the FIFO memory is controlled according to software programmed in a CPU, the efficiency of data processing is increased as a whole, but the data processing is still too time consuming to apply it to a faster printer.
As a conventional controller, there has been known a controller comprised of one CPU or comprised of multiple CPUs which are connected to a common RAM.
In those systems, packet processing of received data and imaging of the received data are executed by one CPU. Since these procedures are executed in a time-division mode by the one CPU, they are executed intermittently. This slows down the data processing.
In a conventional controller having one CPU, a ring buffer is used as an internal memory and a FIFO memory is formed as software by controlling the ring buffer with use of control programs provided therefor. However, in the controller of this type, it is difficult to speed up the data processing since it takes a relatively long time to control the ring buffer.
Furthermore, even in a conventional controller comprised of multiple CPUs which possesses the common RAM used commonly in the time-division system, fast transmission of data of a large volume is impossible since data access has to be done synchronously with time-division clocks.